This page is derived from the GNU Make Manual
Trail Index | More | Makefiles
Make utility and Makefiles
The make utility automatically determines which pieces of a large program based on (multiple object files and library files) need to be recompiled, and issues commands to recompile them. You need a file called a makefile to tell make what to do.
Suppose you are busy with the development of a complicated application, there may be many source files (*.c, *.cc, *.c++,*.f etc) and header files (*.h) that need to be recompiled to produce object files (machine code, *.o).
gcc -c src1.c
gcc -c src2.c
gcc -c myprog.c
gcc myprog.o src1.o src2.o -L /opt/root/lib -lroot -o myprog
These object files must then be linked together with the default libraries, as well as other libraries, like in the example above.
The compile and link comands will become very cumbersome. You may get the program working with one version of the compile-link instruction, but not others. In some weeks time, coming back to your development after a period of absence, you may find you can no longer get your code working, as you cannot remember exactly the compile-link details which were succesful.
Also, if there is only one compile-link instruction, it will reprocess everything in the instruction, even if you only made one small change to just one of the source files. This can be time consuming for large development applications.
The make utility will manage all this complexity. In general, if a C source file has changed, each changed C source file must be recompiled. If a header file has changed, each C source file that includes the header file must be recompiled to be safe. Each compilation produces an object file corresponding to the source file.
Finally, if any source file has been recompiled, all the object files, whether newly made or saved from previous compilations, must be linked together to produce the new executable program.
What a Rule Looks Like
A simple makefile consists of rules with the following shape:
TARGET ... : PREREQUISITES ...
COMMAND
...
...
- A target is usually the name of a file that is generated by a program; examples of targets are executable or object files. A target can also be the name of an action to carry out, such as `clean' (*note Phony Targets::).
- A prerequisite is a file that is used as input to create the target. A target often depends on several files.
- A command is an action that
make carries out. A rule may have more than one command, each on its own line.
- Please note: you need to put a tab character at the beginning of every command line! This is an obscurity that catches the unwary.
Usually a command is in a rule with prerequisites and serves to create a target file if any of the prerequisites change. However, the rule that specifies commands for the target need not have prerequisites. For example, the rule containing the delete command associated with the target `clean' does not have prerequisites. A "rule", then, explains how and when to remake certain files which are the targets of the particular rule. `make' carries out the commands on the prerequisites to create or update the target. A rule can also explain how and when to carry out an action.
Note Writing Rules: Rules.
A makefile may contain other text besides rules, but a simple makefile need only contain rules. Rules may look somewhat more complicated than shown in this template, but all fit the pattern more or less.
A Simple Makefile
Here is a straightforward makefile that describes the way an executable file called `edit' depends on eight object files which, in turn, depend on eight C source and three header files.
In this example, all the C files include defs.h, but only those defining editing commands include command.h, and only low level files that change the editor buffer include `buffer.h'.
edit : main.o kbd.o command.o display.o \
insert.o search.o files.o utils.o
cc -o edit main.o kbd.o command.o display.o \
insert.o search.o files.o utils.o
main.o : main.c defs.h
cc -c main.c
kbd.o : kbd.c defs.h command.h
cc -c kbd.c
command.o : command.c defs.h command.h
cc -c command.c
display.o : display.c defs.h buffer.h
cc -c display.c
insert.o : insert.c defs.h buffer.h
cc -c insert.c
search.o : search.c defs.h buffer.h
cc -c search.c
files.o : files.c defs.h buffer.h command.h
cc -c files.c
utils.o : utils.c defs.h
cc -c utils.c
clean :
rm edit main.o kbd.o command.o display.o \
insert.o search.o files.o utils.o
We split each long line into two lines using backslash-newline; this is like using one long line, but is easier to read.
To use this makefile to create the executable file called `edit', type:
make
To use this makefile to delete the executable file and all the object files from the directory, type:
make clean
In the example makefile, the targets include the executable file edit, and the object files main.o and kbd.o. The prerequisites are files such as main.c and defs.h. In fact, each .o file is both a target and a prerequisite. Commands include cc -c main.c and cc -c kbd.c.
When a target is a file, it needs to be recompiled or relinked if any of its prerequisites change. In addition, any prerequisites that are themselves automatically generated should be updated first. In this example, edit depends on each of the eight object files; the object file main.o depends on the source file main.c and on the header file defs.h.
A shell command follows each line that contains a target and prerequisites. These shell commands say how to update the target file. A tab character must come at the beginning of every command line to distinguish commands lines from other lines in the makefile. (Bear in mind that make does not know anything about how the commands work. It is up to you to supply commands that will update the target file properly. All make does is execute the commands in the rule you have specified when the target file needs to be updated.)
The target clean is not a file, but merely the name of an action.
Since you normally do not want to carry out the actions in this rule, clean is not a prerequisite of any other rule. Consequently, make never does anything with it unless you tell it specifically. Note that this rule not only is not a prerequisite, it also does not have any prerequisites, so the only purpose of the rule is to run the specified commands. Targets that do not refer to files but are just actions are called "phony targets".
How make Processes a Makefile
By default, make starts with the first target (not targets whose names start with `.'). This is called the "default goal". ("Goals" are the targets that make strives ultimately to update. *Note Arguments to Specify the Goals: Goals.)
In the simple example of the previous section, the default goal is to update the executable program `edit'; therefore, we put that rule first. Thus, when you give the command:
make reads the makefile in the current directory and begins by processing the first rule.
In the example, this rule is for relinking edit; but before `make' can fully process this rule, it must process the rules for the files that edit depends on, which in this case are the object files. Each of these files is processed according to its own rule. These rules say to update each .o file by compiling its source file.
The recompilation must be done if the source file, or any of the header files named as prerequisites, is more recent than the object file, or if the object file does not exist.
The other rules are processed because their targets appear as prerequisites of the goal. If some other rule is not depended on by the goal (or anything it depends on, etc.), that rule is not processed, unless you tell `make' to do so (with a command such as `make clean').
Before recompiling an object file, `make' considers updating its prerequisites, the source file and header files. This makefile does not specify anything to be done for them - the `.c' and `.h' files are not the targets of any rules - so `make' does nothing for these files. But `make' would update automatically generated C programs, such as those made by Bison or Yacc, by their own rules at this time. After recompiling whichever object files need it, `make' decides whether to relink `edit'. This must be done if the file `edit' does not exist, or if any of the object files are newer than it. If an object file was just recompiled, it is now newer than `edit', so `edit' is relinked.
Thus, if we change the file `insert.c' and run `make', `make' will compile that file to update `insert.o', and then link `edit'. If we change the file `command.h' and run `make', `make' will recompile the object files `kbd.o', `command.o' and `files.o' and then link the file `edit'.
Variables Make Makefiles Simpler
In our example, we had to list all the object files twice in the rule for `edit' (repeated here):
edit : main.o kbd.o command.o display.o \
insert.o search.o files.o utils.o
cc -o edit main.o kbd.o command.o display.o \
insert.o search.o files.o utils.o
Such duplication is error-prone; if a new object file is added to the system, we might add it to one list and forget the other. We can eliminate the risk and simplify the makefile by using a variable. "Variables" allow a text string to be defined once and substituted in multiple places later (*note How to Use Variables: Using Variables.).
It is standard practice for every makefile to have a variable named `objects', `OBJECTS', `objs', `OBJS', `obj', or `OBJ' which is a list of all object file names. We would define such a variable `objects' with a line like this in the makefile:
objects = main.o kbd.o command.o display.o \
insert.o search.o files.o utils.o
Then, each place we want to put a list of the object file names, we can substitute the variable's value by writing `$(objects)' (*note How to Use Variables: Using Variables.).
Here is how the complete simple makefile looks when you use a variable for the object files:
objects = main.o kbd.o command.o display.o \
insert.o search.o files.o utils.o
edit : $(objects)
cc -o edit $(objects)
main.o : main.c defs.h
cc -c main.c
kbd.o : kbd.c defs.h command.h
cc -c kbd.c
command.o : command.c defs.h command.h
cc -c command.c
display.o : display.c defs.h buffer.h
cc -c display.c
insert.o : insert.c defs.h buffer.h
cc -c insert.c
search.o : search.c defs.h buffer.h
cc -c search.c
files.o : files.c defs.h buffer.h command.h
cc -c files.c
utils.o : utils.c defs.h
cc -c utils.c
clean :
rm edit $(objects)
Using implicit rules and variables to further simplify the Makefile
Any modern version of make, and in particular the GNU version on Linux, does actually know something about most common operations done to create a program; so, if you just specify a dependence like
file.o:file.c file.h anotherfile.h
it will automatically use a command
$(CC) $(CFLAGS) -c file.c
GNU make has even more aces in its sleeves, amongst which the automatic variables like $^, $@ etc are most useful, as they allow for very "clean" makefiles:
target = edit
objects = main.o kbd.o command.o display.o \
insert.o search.o files.o utils.o
$(target) : $(objects) someotherfile.o
$(CC) $^ -o $@
main.o : defs.h
kbd.o : defs.h command.h
command.o : defs.h command.h
display.o : defs.h buffer.h
insert.o : defs.h buffer.h
search.o : defs.h buffer.h
files.o : defs.h buffer.h command.h
utils.o : defs.h
clean :
rm $(target) $(objects)
You can read all about this and more on make by typing on the command line
< Templates | Trail Index | Compiler >
